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cmos dram KM44C4005C, km44c4105c this is a family of 4,194,304 x 4 bit quad cas with extended data out mode cmos drams. extended data out mode offers high speed random access of memory cells within the same row, so called hyper page mode. refresh cycle (2k ref. or 4k ref.), access time (-5 or -6), power consumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. a ll of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self-refresh operation is avail- able in l-version. four separate cas pins provide for seperate i/o operation allowing this device to operate in parity mode. this 4mx4 extended data out quad cas dram family is fabricated using samsung s advanced cmos process to realize high band- width, low power consumption and high reliability. ? part identification - KM44C4005C/c-l (5v, 4k ref.) - km44c4105c/c-l (5v, 2k ref.) ? extended data out mode operation (fast page mode with extended data out) ? four separate cas pins provide for separate i/o operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? fast parallel test mode capability ? ttl compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in plastic soj and tsop(ii) packages ? single +5v 10% power supply control clocks ras cas 0 - 3 w vcc vss dq0 to dq3 a0-a11 (a0 - a10) *1 a0 - a9 (a0 - a10) *1 memory array 4,194,304 x 4 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 4m x 4bit cmos quad cas dram with extended data out description features functional block diagram ? refresh cycles part no. refresh cycle refresh period normal l-ver c4005c 4k 64ms 128ms c4105c 2k 32ms ? performance range speed t rac t cac t rc t hpc -5 50ns 13ns 84ns 20ns -6 60ns 15ns 104ns 25ns ? active power dissipation speed refresh cycle 4k 2k -5 495 605 -6 440 550 unit : mw s e n s e a m p s & i / o data out buffer data in buffer oe note) *1 : 2k refresh col. address buffer row address buffer refresh counter refresh control refresh timer column decoder row decoder vbb generator
cmos dram KM44C4005C, km44c4105c pin configuration (top views) pin name pin function a0 - a11 address inputs (4k product) a0 - a10 address inputs (2k product) dq0 - 3 data in/out v ss ground ras row address strobe cas 0~ cas 3 column address strobe w read/write input oe data output enable v cc power(+5.0v) n.c no connection v cc dq0 dq1 w ras *a11(n.c) cas 0 cas 1 a10 a0 a1 a2 a3 v cc v ss dq3 dq2 cas 3 oe a9 cas 2 n.c a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc dq0 dq1 w ras *a11(n.c) cas 0 cas 1 a10 a0 a1 a2 a3 v cc v ss dq3 dq2 cas 3 oe a9 cas 2 n.c a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 *a11 is n.c for km44c4105c(5v, 2k ref. product) k : 300mil 28 soj s : 300mil 28 tsop ii ? km44c40(1)05ck ? km44c40(1)05cs
cmos dram KM44C4005C, km44c4105c absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol rating units voltage on any pin relative to v ss v in, v out -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -1.0 to +7.0 v storage temperature tstg -55 to +150 c power dissipation p d 1 w short circuit output current i os 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +2.0v/20ns, pulse width is measured at v cc *2 : -2.0/20ns, pulse width is measured at v ss parameter symbol min typ max units supply voltage v cc 4.5 5.0 5.5 v ground v ss 0 0 0 v input high voltage v ih 2.4 - v cc +1.0 *1 v input low voltage v il -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) parameter symbol min max units input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
cmos dram KM44C4005C, km44c4105c *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 and i cc6 address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one hyper page mode cycle time, t hpc . dc and operating characteristics (continued) i cc1 * : operating current ( ras and cas cycling @t rc =min.) i cc2 : standby current ( ras = cas = w =v ih ) i cc3 * : ras -only refresh current ( cas =v ih , ras cycling @t rc =min.) i cc4 * : hyper page mode current ( ras =v il , cas , address cycling @t hpc =min.) i cc5 : standby current ( ras = cas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras and cas cycling @t rc =min.) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, cas =0.2v, dq=don t care, t rc =31.25us(4k/l-ver), 62.5us(2k/l-ver), t ras =t ras min~300ns i ccs : self refresh current ras = cas =0.2v, w = oe =a0 ~ a11=v cc -0.2v or 0.2v, dq0 ~ dq3=v cc -0.2v, 0.2v or open symbol power speed max units KM44C4005C km44c4105c i cc1 don t care -5 -6 90 80 110 100 ma ma ma i cc2 normal l don t care 2 1 2 1 ma ma i cc3 don t care -5 -6 90 80 110 100 ma ma ma i cc4 don t care -5 -6 80 70 90 80 ma ma ma i cc5 normal l don t care 1 250 1 250 ma ua i cc6 don t care -5 -6 90 80 110 100 ma ma ma i cc7 l don t care 300 300 ua i ccs l don t care 250 250 ua
cmos dram KM44C4005C, km44c4105c capacitance (t a =25 c, v cc =5v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a11] c in1 - 5 pf input capacitance [ ras , cas x, w , oe ] c in2 - 7 pf output capacitance [dq0 - dq3] c dq - 7 pf test condition : v cc =5.0v 10%, vih/vil=2.4/0.8v, voh/vol=2.0/0.8v parameter symbol -5 -6 units notes min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 106 140 ns access time from ras t rac 50 60 ns 3,4,10 access time from cas t cac 13 15 ns 3,4,5,20 access time from column address t aa 25 30 ns 3,10 cas to output in low-z t clz 3 3 ns 3,20 output buffer turn-off delay from cas t cez 3 13 3 15 ns 6,13 oe to output in low-z t olz 3 3 ns 3 transition time (rise and fall) t t 2 50 2 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 13 15 ns 16 cas hold time t csh 38 45 ns 19 cas pulse width t cas 8 10k 10 10k ns 25 ras to cas delay time t rcd 20 37 20 45 ns 4,18 ras to column address delay time t rad 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 ns 17 row address set-up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set-up time t asc 0 0 ns 18 column address hold time t cah 8 10 ns 18 column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold time referenced to cas t rch 0 0 ns 8,17 read command hold time referenced to ras t rrh 0 0 ns 8 write command hold time t wch 10 10 ns 16 write command pulse width t wp 10 10 ns write command to ras lead time t rwl 13 15 ns write command to cas lead time t cwl 8 10 ns 19 ac characteristics (0 c t a 70 c, see note 1,2)
cmos dram KM44C4005C, km44c4105c ac characteristics (continued) parameter symbol -5 -6 units notes min max min max data set-up time t ds 0 0 ns 9 data hold time t dh 8 10 ns 9 refresh period (2k, normal) t ref 32 32 ms refresh period (4k, normal) t ref 64 64 ms refresh period (l-ver) t ref 128 128 ms write command set-up time t wcs 0 0 ns 7,18 cas to w delay time t cwd 30 34 ns 7,16 ras to w delay time t rwd 67 79 ns 7 column address to w delay time t awd 42 49 ns 7 cas precharge to w delay time t cpwd 47 54 ns 7 cas set-up time ( cas -before- ras refresh) t csr 5 5 ns 18 cas hold time ( cas -before- ras refresh) t chr 10 10 ns 17 ras to cas precharge time t rpc 5 5 ns 18 access time from cas precharge t cpa 28 35 ns 3,17 hyper page mode cycle time t hpc 20 24 ns 14,21 hyper page read-modify-write cycle time t hprwc 62 71 ns 14,21 cas precharge time (hyper page cycle) t cp 8 10 ns 22 ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns oe access time t oea 13 15 ns 23 oe to data delay t oed 13 15 ns 24 output buffer turn off delay time from oe t oez 3 13 3 15 ns 6 oe command hold time t oeh 13 15 ns write command set-up time (test mode in) t wts 10 10 ns 11 write command hold time (test mode in) t wth 10 10 ns 11 w to ras precharge time( c -b- r refresh) t wrp 10 10 ns w to ras hold time( c -b- r refresh) t wrh 10 10 ns output data hold time t doh 5 5 ns output buffer turn off delay from ras t rez 3 13 3 15 ns 6,13 output buffer turn off delay from w t wez 3 13 3 15 ns 6 w to data delay t wed 15 15 ns oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width (hyper page cycle) t wpe 5 5 ns ras pulse width ( c -b- r self refresh) t rass 100 100 us 27,28,29 ras precharge time ( c -b- r self refresh) t rps 90 110 ns 27,28,29 cas hold time ( c -b- r self refresh) t chs -50 -50 ns 27,28,29 hold time cas low to cas high t clch 5 5 ns 15,26
cmos dram KM44C4005C, km44c4105c test mode cycle parameter symbol -5 -6 units notes min max min max random read or write cycle time t rc 89 109 ns read-modify-write cycle time t rwc 121 145 ns access time from ras t rac 55 65 ns 3,4,10,12 access time from cas t cac 18 20 ns 3,4,5,12 access time from column address t aa 30 35 ns 3,10,12 ras pulse width t ras 55 10k 65 10k ns cas pulse width t cas 13 10k 15 10k ns ras hold time t rsh 18 20 ns cas hold time t csh 43 50 ns column address to ras lead time t ral 30 35 ns cas to w delay time t cwd 35 39 ns 7 ras to w delay time t rwd 72 84 ns 7 column address to w delay time t awd 47 54 ns 7 cas precharge to w delay time t cpwd 52 59 ns 7 hyper page mode cycle time t hpc 25 30 ns 14 hyper page read-modify-write cycle time t hprwc 52 61 ns 14 ras pulse width (hyper page cycle) t rasp 55 200k 65 200k ns access time from cas precharge t cpa 33 40 ns 3 oe access time t oea 18 20 ns oe to data delay t oed 18 20 ns oe command hold time t oeh 18 20 ns ( note 11 )
cmos dram KM44C4005C, km44c4105c notes an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 2ns for all inputs. measured with a load equivalent to 2 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes the t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are non restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min), then the cycle is a read- modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. t rch and t rrh must be satisfied for a read cycle. these parameters are referenced to the first cas falling edge in early write cycles and to w falling edge in oe controlled write cycle and read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . these specifications are applied in the test mode. in test mode read cycle, the values of t rac, t aa and t cac are delayed by 2ns to 5ns for the specified values. these parame- ters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet. if ras goes high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes high before ras high going, the open circuit condition of the output is achieved by ras high going. t asc 3 6ns, assume t t = 2.0ns. in order to hold the address latched by the first cas going low, the parameter t clch must be met. the last cas x edge to go low. the last cas x edge to go high. the first cas x edge to go low. the first cas x edge to go high. output parameter is refrenced to corresponding cas x input. the last rising cas x edge to next cycle s last rising cas x edge. the last rising cas x edge to first falling cas x edge. the first dqx controlled by the first cas x to go low. the last dqx controlled by the last cas x to go high. each cas x must meet minimum pulse width. the last falling cas x edge to the first rising cas x edge. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 4096(4k)/2048(2k) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval, cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 8. 6. 5. 10. 9. 3. 2. 1. 4. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 11. 12. 13. 25. 26. 27. 28. 29. 7.
cmos dram KM44C4005C, km44c4105c t crp ras v ih - v il - cas0 v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3 read cycle column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t aa t oea t cac t clz t rac open t rrh t rch don t care undefined t rcs t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch t rez t oez t cez t wez data-out t olz t roh
cmos dram KM44C4005C, km44c4105c t wcs write cycle ( early write ) note : d out = open a v ih - v il - w v ih - v il - oe v ih - v il - row address t ral t rad t asr t rah t asc t cah t wp t ds t dh t wch don t care data-in undefined t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch v ih - v il - dq0 ~ dq3 column address t csh
cmos dram KM44C4005C, km44c4105c t oed a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3 column address row address t ral t rad t asr t rah t asc t cah data-in t wp don t care write cycle ( oe controlled write ) note : d out = open t cwl t rwl t ds t dh t oeh undefined t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch
cmos dram KM44C4005C, km44c4105c w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3 valid t wp don t care read - modify - wrtie cycle t rwl t cwl t oez t oed t awd t cwd data-out undefined valid data-in t rac t aa t ds t dh t crp ras v ih - v il - cas0 v ih - v il - t ras t rc t crp t rp t csh t rsh t rcd t cas t crp cas1 v ih - v il - t crp cas2 v ih - v il - t crp cas3 v ih - v il - t clch a v ih - v il - row address t ral t rad t asr t rah t asc t cah t oea t rwd column address t cac t clz t olz
cmos dram KM44C4005C, km44c4105c dq0 dq1 dq2 dq3 t rch t oez t clz ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row addr t rhcp t rasp t cas t asc t rad t asr t rah t crp valid don't care hyper page mode read cycle t oez t rrh data-out undefined valid data-out column address column address t rsh t cas t rcd t hpc ? t cah ? ? ? t rch ? t rcs t rcs t rcs t oea t clz t aa t oez t rac t aa ? ? t cp t cas t rp t cp v ih - v il - v ih - v il - v ih - v il - cas0 cas1 cas2 cas3 ? ? t clch t asc v ih - v il - v ih - v il - v ih - v il - t hpc t cpa t aa t cpa t cac ? t clz valid data-out valid data-out valid data-out valid data-out valid data-out ? valid data-out t clch t rch t olz t csh t asc t ral t rac t clz ? ? t cah t cah t asc
cmos dram KM44C4005C, km44c4105c t asc t cah ras v ih - v il - cas0 v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row addr t rhcp t rasp t cas t rad t asr t rah t asc t crp valid don t care hyper page mode write cycle ( early write ) data-in undefined valid data-in t ds note : d out = open column address t rsh t cas t rcd t hpc ? t csh t cah t asc ? ? ? t wcs t wch t wcs t wp t wp t wch t wcs t wch t dh t ds t dh t ds ? ? ? t rp t cp t cp t cas t hpc cas1 v ih - v il - t cas ? t cas cas2 v ih - v il - t cas ? t cas cas3 v ih - v il - t cas ? v ih - v il - valid data-in t ds valid data-in t dh t ds v ih - v il - valid data-in valid data-in t ds t dh t ds t dh v ih - v il - valid data-in t ds dq0 dq1 dq2 dq3 t dh t dh valid data-in t dh ? ? ? ? ? ? ? ? t wp column address t cah
cmos dram KM44C4005C, km44c4105c t cac t asc t asc ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3 row addr t rasp t asr valid don t care hyper page read - modify - write cycle data-out undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t cah t ral t prwc t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t aa t rac t oea t clz t cac t oez t oed valid data-in valid data-out valid data-in t clz t ds t oea t aa t dh t ds t oez t oed t rwl t rp t rsh t rah t clch t cas t cas t cas t cas cas0 v ih - v il - cas1 v ih - v il - cas2 v ih - v il - cas3 v ih - v il - t clch t cwl t csh
cmos dram KM44C4005C, km44c4105c ras v ih - v il - casx v ih - v il - a v ih - v il - row addr t ras t rc t rp t asr t rah t crp don t care ras - only refresh cycle* undefined note : w , oe , d in = don t care d out = open t rpc t crp cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - casx v ih - v il - t ras t rc t rp t wrp t rpc t rp t cp t chr t csr w v ih - v il - t wrh t cez t rpc v ih - v il - dq0 ~ dq3 open
cmos dram KM44C4005C, km44c4105c t cez ras v ih - v il - casx v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dqx hidden refresh cycle ( read ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp t rcs t aa t oea t cac t clz t rac open don t care t rsh t oez undefined t rc data-out t rp t rp t ras t wrh
cmos dram KM44C4005C, km44c4105c ras v ih - v il - casx v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - hidden refresh cycle ( write ) column address row address t ras t rc t chr t rcd t rad t asr t rah t asc t cah t crp don t care t rsh data-in undefined t rc note : d out = open t wch t wp t dh t rp t rp t ras t ds t wcs dqx t wrh t wrp
cmos dram KM44C4005C, km44c4105c don t care undefined cas - before - ras self refresh cycle note : oe , a = don t care, we =vcc-0.2v ras v ih - v il - casx v ih - v il - t rass t rps t rpc t chs t rp t cp t csr t cez t rpc open v oh - v ol - dq0 ~ dq3 test mode in cycle note : oe , a = don t care ras v ih - v il - casx v ih - v il - t ras t rc t rp t crp t wts t rpc t rp t cp t chr t csr w v ih - v il - t wth t cez open v ih - v il - dq0 ~ dq3
cmos dram KM44C4005C, km44c4105c package dimension 28 soj 300mil 0 . 3 0 0 ( 7 . 6 2 ) 0 . 3 3 0 ( 8 . 3 9 ) 0 . 3 4 0 ( 8 . 6 3 ) 0.730 (18.54) 0.720 (18.30) max 0.741 (18.82) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.0375 (0.95) 0.050 (1.27) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 2 8 0 ( 7 . 1 1 ) 0 . 2 6 0 ( 6 . 6 1 ) min #28 #1 units : inches (millimeters) 28 tsop(ii) 300mil max 0.047 (1.20) min 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) 0.050 (1.27) 0.037 (0.95) 0.721 (18.31) 0.729 (18.51) 0.741 (18.81) max 0.010 (0.25) 0.004 (0.10) 0 . 3 0 0 ( 7 . 6 2 ) 0 . 3 7 1 ( 9 . 4 2 ) 0 . 3 5 5 ( 9 . 0 2 ) units : inches (millimeters) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o

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